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The code is still fairly vendor-dependent, since the only hardware we've had the opportunity to try is Altera's APEX20K200E. Quartus II is the EDA tool required to compile designs for the APEX20K family of FPGAs. A limited version is available for free from Altera's web site. The web edition can not target chips larger than the APEX20K160, so if you are interested in actually testing the design in hardware, you will have to purchase or have access to a full edition. You can still compile the design and simulate it using the web edition, however.
Please note that Quartus II is incredibly memory intensive and you will require at least 256MB of memory to compile the entire design, and more if you want to do so in a reasonable amount of time. Last time we checked it took 30 minutes to compile the entire design on a PIII 666 with 384MB of SDRAM running Windows 2000. Quartus' performance also seems to be best under Windows 2000, and worse under Windows 98.
The design was initially tested on Altera's Excalibur Development Kit. The board has a built-in SODIMM connector and uses the APEX20K200E (EPF20K200EFC484). The design is guaranteed to work with this board and FPGA. Other boards and FPGAs may or may not work. If you manage to port the design to different hardware please let us know and we will add your hardware to this list.
You will also need a 144-pin SODIMM (commonly found in laptops). 32MB PC66 memory should suffice.
You will need a DAC of some sort as well. We used a simple resistor network (see here for details), although a VDAC should work equally well.