fifo chaos

[benjcarson at digitaljunkies.ca]

The fifo had no latency that I know of.  It was dual ported however, but 
since the two clocks were related to one another we got away with not having 
to synchronize (pipeline) the inputs and outputs. 

I wasn't aware that lpm_ram had latency associated with it other than the 
fact that data shows up on the wires one cycle after a read signal is 
asserted. 


Benj 


Jeff Mrochuk writes: 

> fifo appears to be working, more extensive testing required. 
> 
> So did the altera fifo have a read latency?  The LPM_RAM has a two cycle
> latency, which isn't a big issue.  It means one line will take 642
> cycles to read instead of 640 
> 
> Jeff
> --