FIFO issues

[benjcarson at digitaljunkies.ca]

Another thought: we should probably look into seeing if we can get a sample 
of a RAMDAC and move some of our FIFOs off the FPGA.  That might solve some 
issues and free us from using Altera-specific stuff.  All at the cost of 
more interfacing though.  Whoopee! 

Next time I've got a spare minute or two at work I'll have a look at Digikey 
and see what I can dig up... 


Benj 

Jeff Mrochuk writes: 

> Here's one for ya.
>  
> I tried to compile my fifo, and even with only 32x8 its gigantic (14% of our 
> chip)
> So I took a look at their design and it turns out the reason its so small is 
> because it uses ESB bits.  If you disable ESB bits on the altera fifo, our 
> 640x8 fifo is 103% of the chip.
>  
> Looks like we may have to be a bit more creative in our display, maybe empty 
> it as it fills.  I'd like to know how commercial hardware does it, maybe it 
> just has giant fifo hardware.
>  
> In the mean time, do you know if you can tell quartus to use ESB bits on your 
> own designs?
>  
> Jeff 
> 
>