[bf1942] Sparc
Stan Hoeppner
Stan at hardwarefreak.com
Tue Jun 3 03:25:24 EDT 2003
> I stand corrected. Still, the big argument for RISC was that
> the simpler
> atomic instructions could be executed with a faster clock,
> allowing the
> same amount of work to happen in the same amount of time on a
> simpler and
> cooler-running CPU.
Absolutely. And for a very long time, all the RISC chips outperformed x86
and 680x0. IMHO, RISC has been very successful. There were two minor
downsides: application binaries were somewhat larger, requiring more
storage space (RAM & disk), and the overall system bus architectures needed
to be somewhat faster than the CISC designs in order to get the larger
volume of smaller/simpler instructions into the CPU. With the debut of the
NextGen Nx586, then the Pentium Pro (and now all the x86 CPUs, except
Cyrix/VIA possibly), we got CISC CPUs with RISC cores. So today, we have
the best of both worlds: the somewhat more svelt code of CISC with the
performance of RISC.
> BTW, for x86, DJNZ is done with a LOOP instruction, possibly with a
> condition code modifier. "LOOP" means "decrement CX and loop
> while CX is
> not zero". (ECX for 32 bit code, CX for 16 bit.) I think
> "DJNZ" is the
> mnemonic for 68000 and Z80 processors.
Heheh, apparently you have quite a bit more experience with assembly than I
do. You're absolutely correct on DJNZ. I took an assembly course back in
... 1986. It was 8080/Z80 assembly. DJNZ is an 8080 instruction. The Z80
used the 8080 instruction set, but was a faster clocked part from Zylog, the
8080 being an Intel part. The machines were Radio Shack TRS-80 (trash 80)
model IIIs. And, coincidentally, ALL binaries were *small* back then. ;)
> The ADI SHARC (a VLIW DSP) uses a "zero-overhead" loop system
> in which a
> setup instruction loads helper registers with the loop count and last
> instruction of the loop. When the instruction pointer hits the last
> address, it automatically decrements the counter and jumps to the
> instruction following the setup instruction, in parallel with
> the last
> instruction, effectively taking zero cycles. The counter and
> jump address
> are hardware stacks, allowing a small degree of loop nesting.
Interesting, and efficient, as I guess DSPs really need to be.
StanTheMan
TheHardwareFreak
stan at hardwarefreak.com
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