[bf1942] Sparc

ScratchMonkey ScratchMonkey at SewingWitch.com
Mon Jun 2 13:12:14 EDT 2003

--On Monday, June 02, 2003 9:45 AM -0500 Stan Hoeppner 
<Stan at hardwarefreak.com> wrote:

> SPARC (Scalable Processor ARChitecture) is a fairly clean RISC
> architecture, and thus it will take quite a few SPARC machine
> instructions per x86 instruction, in some cases.  For loads and stores,
> it's probably a one-to-one ratio.  In nasty cases, like say DJNZ (if this
> is still a valid x86 instruction--been a while since I dealt with
> assembly), it would take many SPARC instructions..

I stand corrected. Still, the big argument for RISC was that the simpler 
atomic instructions could be executed with a faster clock, allowing the 
same amount of work to happen in the same amount of time on a simpler and 
cooler-running CPU.

BTW, for x86, DJNZ is done with a LOOP instruction, possibly with a 
condition code modifier. "LOOP" means "decrement CX and loop while CX is 
not zero". (ECX for 32 bit code, CX for 16 bit.) I think "DJNZ" is the 
mnemonic for 68000 and Z80 processors.

The ADI SHARC (a VLIW DSP) uses a "zero-overhead" loop system in which a 
setup instruction loads helper registers with the loop count and last 
instruction of the loop. When the instruction pointer hits the last 
address, it automatically decrements the counter and jumps to the 
instruction following the setup instruction, in parallel with the last 
instruction, effectively taking zero cycles. The counter and jump address 
are hardware stacks, allowing a small degree of loop nesting.

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