[Bug 3427] New: Single Player causes SIGBUS on SGI IRIX

bugzilla-daemon at icculus.org bugzilla-daemon at icculus.org
Thu Nov 15 02:29:57 EST 2007


http://bugzilla.icculus.org/show_bug.cgi?id=3427

           Summary: Single Player causes SIGBUS on SGI IRIX
           Product: Quake 3
           Version: SVN HEAD
          Platform: SGI
        OS/Version: IRIX
            Status: NEW
          Severity: critical
          Priority: P3
         Component: Platform
        AssignedTo: zakk at icculus.org
        ReportedBy: baggett.patrick at figglesoftware.com
         QAContact: quake3-bugzilla at icculus.org


Creating a single player game under SGI IRIX causes a SIGBUS to be raised and
the game aborts. This seems to be caused by the code in botlib/l_precomp.c.
Since I have heard that other RISC ports of Quake3 (PowerPC, SPARC) are having
a similar problem (though I can't confirm it), it seems quite clear that
RISC-based machines are hitting unaligned data (the source of SIGBUS).

Looking into l_precomp.c(1616):
typedef struct value_s
{
        signed long int intvalue;
        double floatvalue;
        int parentheses;
        struct value_s *prev, *next;
} value_t;

Reading "floatvalue" will raise SIGBUS on a RISC machine since it is not 8-byte
aligned. On a 64-bit port, the pointers "prev" and "next" are also unaligned.

The following is a more optimal ordering:
typedef struct value_s
{
        double floatvalue;
        struct value_s *prev, *next;
        signed long int intvalue;
        int parentheses;
} value_t;


The first field is 8-byte aligned, the next two are aligned in both 32- and
64-bit builds, the long int (which is 64 bits on ILP64 and 32 bits on ILP32) is
also aligned to its natural polymorphic boundary, and finally, the 32-bit
integer is aligned. There are probably a few other RISC-unfriendly structures
being used, though certainly even x86 processors would benefit from data that
is naturally aligned.

I am currently working on a fix for this under SGI IRIX. It would be
interesting to see if other RISC architectures have their problem solved.
Reported against SVN revision 1212.

Patrick Baggett
Figgle Software


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