SDRAM Controller

Description

This is a low level SDRAM controller, it works well for basic reads, writes, refreshes, address multiplexing and initialization, but may require extensions for certain SDRAM features.

This module was written for an EE552 Project which required the use of the SODIMM slot on the Altera NIOS Excalibur board. The design, however, should work on any device connected to SDRAM.

Documentation

The code is not well documented due to time constraints, hopefully it can be updated. The source however at this point is quite easy to follow.

There is some constants at the top to be aware of, for timing concerns, the current code is set up for 50MHz, which requires the use of the PLL on the Nios board.

If you are not familiar with how SDRAM operates we have prepared some recommended reading, so you can understand our source. The following is a list of the most useful links we found.

ARS Technica RAM guide (Part 1,Part 2,Part 3)

Hynix SDRAM Operation Docs

Motorola Microcontroller Documentation (Contains good SDRAM info)

Any questions can be sent to the code's authors Jeff Mrochuk or Benj Carson

Specifications

The current code is not very generic, but should not require much to change the current specifications:

CAS latency 2

Burst Length 4

Clock Frequency 50MHz

It was tested and verified on a 32MB AzenRAM SODIMM.

Source

The code is licensed with OpenCores' OpenIP license. A copy of that license is available here.

Basically it means you can use it freely, and modify it to your needs, as long as that modification is also open source and available.

You can grab the code here: sdram_control.vhd

Last modified: Fri Apr 12 14:10:29 MDT 2002