[manticore] Re: fifo chaos

[Jeff Mrochuk]

Yep, I'm using Dual Ported dual clock ram, the only issue is that my
pointers need to be controlled by the clock.  I'll have to have the end
pointer on one clock, and the start on the other clock.  May make for
some interesing stuff.

Jeff

On Fri, Jun 07, 2002 at 10:54:31AM -0600, benjcarson at digitaljunkies.ca wrote:
> Yeah, a second clock shouldn't be a problem if the ram is dual-ported.  
> Actually, can't you set some parameters in lpm_ram to get it to handle two 
> different clocks already?  I seem to remember reading that at one point... 
> 
> Benj 
> 
> 
> Jeff Mrochuk writes: 
> 
> >Okay the 8x640 fifo is 119MHz and about 120 (~1%) logic blocks on the
> >20K160E with the same speed grade.  The latency must be in the LPM_RAM,
> >because the data lines connect structurally outside of a process, as are
> >the read and write enables.  I'm also using the dual port ram. 
> >
> >I'll look into it though.  I only have one clock at the moment, but its
> >easy to add another. 
> >
> >Jeff 
> >
> >On Fri, Jun 07, 2002 at 10:04:26AM -0600, benjcarson at digitaljunkies.ca 
> >wrote:
> >>The fifo had no latency that I know of.  It was dual ported however, but 
> >>since the two clocks were related to one another we got away with not 
> >>having to synchronize (pipeline) the inputs and outputs.  
> >>
> >>I wasn't aware that lpm_ram had latency associated with it other than the 
> >>fact that data shows up on the wires one cycle after a read signal is 
> >>asserted.  
> >>
> >>
> >>Benj  
> >>
> >>
> >>Jeff Mrochuk writes:  
> >>
> >>>fifo appears to be working, more extensive testing required. 
> >>>
> >>>So did the altera fifo have a read latency?  The LPM_RAM has a two cycle
> >>>latency, which isn't a big issue.  It means one line will take 642
> >>>cycles to read instead of 640 
> >>>
> >>>Jeff
> >>>--  
> >>
> >
> >-- 
> 

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